The present invention relates to non-volatile semiconductor memory devices having a split-gate structure.
A non-volatile memory transistor with a split-gate structure is known as one of electrically erasable ROMs (EEPROM) having a memory cell that is composed of a single transistor. The non-volatile memory transistor has a floating gate, a control gate and an insulation layer between the floating gate and the control gate. The insulation layer functions as a tunnel insulation layer. In such a non-volatile memory transistor, for example, hot electrons are injected through the gate insulation layer to the floating gate to write data therein. The charge is drawn from the floating gate by Fowler-Nordheim conduction through the tunnel insulation layer to thereby erase the data.
In the case of a non-volatile memory transistor having a split-gate structure, it may be difficult to obtain the silicon oxide layer that functions as a tunnel insulation layer in a predetermined film thickness by, for example, a thermal oxidation method. In such a case, two or more silicon oxide layers are deposited one on top of the other to obtain the required silicon oxide layer. Such a technology is described in, for example, Japanese Laid-open patent application HEI 8-236647. According to the technology described therein, the insulation layer that functions as a tunnel insulation layer is composed of a first silicon oxide layer that is formed by a CVD method and a second silicon oxide layer that is formed by a thermal oxidation method. The non-volatile memory transistor has a structure in which the first silicon oxide layer that is formed by a CVD method contacts the control gate.
In general, when a silicon oxide layer is formed by a CVD method, the film density of the silicon oxide layer is coarse, and the interface state is high and unstable. As a result, when data is to be erased, electrons are likely to be captured by the interface, and the data wiring/erasing cycle life is short, which is presumed to be about 10,000 cycles. In general, a programmable memory device is required to have more than 100,000 cycles. Therefore, the device formed by the conventional technology has a short cycle life, and presents problems in its durability.
One embodiment of the present invention relates to a non-volatile semiconductor memory device including a split-gate structure including a source, a drain, a gate insulation layer, a floating gate, an intermediate insulation layer that functions as a tunnel insulation layer, and a control gate. The intermediate insulation layer includes at least three insulation layers, wherein first and second outermost layers of the three insulation layers respectively contact the floating gate and the control gate, and are composed of silicon oxide layers that are formed by a thermal oxidation method.
Another embodiment relates to a device including non-volatile semiconductor memory region with a split-gate structure. The device includes a source and drain formed in a substrate, and a gate insulation layer. A floating gate is in contact with the gate insulation layer, and an intermediate insulation layer is in contact with a portion of the floating gate. A control gate is in in contact with the intermediate insulation layer. The intermediate insulation includes at least three insulation layers including a first layer that contacts the floating gate, a second layer, and a third layer that contacts the control gate, the second layer being positioned between the first and second layers. The intermediate insulation layer and the control gate have a split-gate structure.